The European Processor Initiative (EPI) is a project with 27 partners from 10 European countries, aiming to achieve Europe’s independence in HPC chip technologies and infrastructure.
The aim of EPI is to design and implement a roadmap for a new family of low-power European processors for extreme-scale computing, high-performance Big Data, and a range of emerging applications.
The EU’s ambition, as defined by the EU Commission, is to increase Europe’s share of global semiconductor production from 10% to 20% over the 2020-2030 timeframe. This includes enhancing manufacturing capacity and improving energy efficiency tenfold by 2030.
Supporting European technological autonomy
The 2024 Draghi report states that the EU has become dependent on non-EU countries for chip technologies, packaging, and assembly, and that it should de-risk its strategic dependencies.
Therefore, through a framework partnership agreement call, the European Commission helped launch EPI in 2018 (with its first phase, EPI SGA1).
This second implementation phase of the EPI continued the initial developments of Phase 1 on European microprocessors and accelerators to support European technological autonomy and sovereignty in this critical area.
Based on a solid, long-term economic approach, the EPI’s ambition is to deliver central components of future European supercomputers capable of tackling societal challenges and boosting innovation and the digital transformation of the European economy and science.
The specific focus of the second phase is to finalise the development of the first generation of low-power microprocessor units and accelerators, enhance existing technologies to target the incoming European Exascale machines, develop the second generation, and ensure paths for industrialisation and commercialisation of these technologies.
27 partners build a new future in two pillars
Starting from the expertise and IP of 27 partners across 10 European countries, EPI’s goal is to materialise in two central pillars – the work on the General Purpose Processor (Rhea GPP) and the European accelerator (EPAC).
The GPP partners work to explore the design space, define requirements, and prepare user validation of these chip technologies. A dedicated company, SiPearl, has been created, with the mission to define, industrialise and produce the expected GPP.
The GPP goal has been defined as the Rhea General Purpose family, with:
- Arm Neoverse V1 cores
- Arm NoC
- Dedicated crypto IP
Europe’s most complex processor ever
The Rhea1 chip is now in production, is expected to be back from tape-out promptly, and will be the most complex processor ever designed in Europe.
EPAC architecture includes RISC-V vector tiles (VTILE), specialised Deep Learning and Stencil accelerators (STX), and variable-precision floating-point cores (VRP), all carefully engineered within a heterogeneous tile architecture whose subunits comply with the RISC-V standardisation efforts.
The RISC-V-based accelerators gather several IPs from several providers on the same chip:
- VPU – Vector Processing Unit
- STX – Stencil/Tensor Accelerator
- VRP – Variable Precision Unit
Outcomes
Working together with two pilot projects (EUPEX and EUPILOT, launched at the same time as EPI phase 2), EPI has:
- Shared EPAC IPs with the EUPILOT project, which taped out in August, and also with the DARE project, which is to become the new EU flagship project targeting RISC-V-based processors.
- Shared with the EUPEX project the Rhea specification, to achieve the preparation of the Rhea-powered blades to be integrated into the JUPITER system in Germany.
